Which of the following is closest to the year when the RISC architecture was first proposed? 1970 1980 1990 2010.
Which of the following is closest to the year when the RISC-V project began? 1970 1980 1990 2010.
What does RISC stand for?
Real Instruction Simple Computing Reduced Instruction Set Computer Register Instruction Stack Computer Raw Implementation of Source Code.
Which of the following is a trait of the RISC architecture?
Memory access is limited to Load and Store instructions. The CPU contains only a few general purpose registers. Most instructions have access to memory. The instruction set is very dense.
RISC-V is the first open RISC ISA.
True False.
What does it mean to say that RISC-V uses a modular rather than incremental design?
The ISA consists of a combination of a base ISA and a set of ISA extensions. The ISA consists of a series of incremental variants where each one includes the previous design, plus some additions. The ISA consists of optional blocks like the ALU, Register File, Datapath, and so on. Actually, the RISC-V ISA uses an incremental design.
What happens if a RISC-V processor fetches code with instructions from extensions that are missing in the physical CPU?
A fatal exception occurs and the execution of instructions cannot continue. An exception occurs, which the software must handle to take some action like emulating the instruction. This situation cannot occur because the compiler guarantees that the generated code will only include instructions supported by the target CPU. The unsupported instructions are simply ignored, doing the same as a NOP instruction would do.
Which of the following is NOT a lifecycle status to indicate the level of maturity of a RISC-V ISA specification?
Finalized Frozen Open Ratified.
How is the RISC-V manual divided into its two volumes?
Volume 1 covers the ratified ISA specifications, and volume 2 covers the open and frozen ISA specifications. Volume 1 covers the base ISAs, and volume 2 covers the ISA extensions. Volume 1 covers the unprivileged ISA, and volume 2 covers the privileged ISA. Actually, the RISC-V manual consists of one single volume.
What is the main difference between the x86 and RISC-V ISAs?
RISC-V has more addressing modes than x86. x86 is a CISC ISA, while RISC-V is a RISC ISA. x86 has much more general purpose CPU registers than RISC-V. x86 has less instructions than RISC-V.
Who owns and regulates the RISC-V ISA?
ARM Holdings Intel Corporation RISC-V International Nobody owns RISC-V, and anyone can modify the specification.
How is it possible for RISC ISAs like those by ARM to be so different from RISC-V?
ARM ISAs have been influenced by industry demands in a similar way as CISC ISAs were in the 1970s. ARM ISAs are based on the CISC philosophy. ARM ISAs are exclusively intended for embedded applications. Actually, all RISC ISAs are very similar.
Which of the following is NOT a way to contribute to RISC-V?
Contributing to maintain the specifications on GitHub. Actually, contribution to RISC-V is not open to the general public. Proposing new instructions to the existing RISC-V base ISAs or any of the ISA extensions. Using the RISC-V ISA in your hardware and paying royalties to RISC-V International for its use.
What does the 32 in RV32I stands for?
The number of CPU registers The width of the address space The width of the CPU registers The width of the decoded immediates The width of the instructions.
RISC-V is the first true open source ISA.
True False.
How are instruction type formats defined?
Grouping instructions by the encoding of immediate Grouping instructions by the number of registers used Grouping instructions by area of functionality.
RV64I adds to RV32I new 64-bit wide instructions specifically for loading and storing 64-bit wide values (Double Words), called LD (Load Doubleword) and SD (Store DoubleWord).
True False.
RV64I adds to RV32I a new instruction specifically for adding two 64-bit wide values and obtaining a 64 bit wide result.
True False.
Can the major opcode unequivocally identify the exact instruction?
Only some instructions are unequivocally identified by the major opcode alone. Never, no instruction is unequivocally identified by the major opcode alone. Always, all instructions are unequivocally identified by the major opcode alone.
One can write RISC-V extensions with 96-bit wide instructions.
True, as long as it has the correct major opcode. True, instruction can be of arbitrary width. False, instructions can only be 32, 64 or 128 bits wide. False, instructions can only be a power of two wide. False, instructions are only 32 bits wide.
All instructions in RV32I and RV64I have "11" as their first two lowest bits.
Only true for some extensions Always true False, only RV32I ones do False, only RV64I ones do False, both RV32I and RV64I ones can have different first two lowest bits.
The instruction add x0 x1 x2, given the current state of the register file [x0 = 0, x1 = 2, x2 = 2] results in:
x0 = 4, x1 = 2, x2 = 2 x0 = 0, x1 = 2, x2 = 2 x0 = 0, x1 = 0, x2 = 0 x0 = 4, x1 = 0, x2 = 0.
The R-type instruction format is the only one to encode three different registers.
True False.
The J-type instructions have the same structure as the B-type instructions, only differing by how the immediate is encoded.
True False.
The meaning of "I" for the I-type instructions is "immediate", since this is the only instruction type to encode immediates.
True False.
The STORE and LOAD instructions both need two registers and an immediate as operators, and are therefore encoded by the same instruction type.
True False, they are encoded in different types differing only by the encoding of the immediate. False, they are encoded in different types with different field structures.
What is the purpose of pseudoinstructions?
Make programming in assembly less cumbersome by providing abstractions and syntactic sugar for repetitive single instructions or groups of instructions. Serve as a guide for making it easier to optimize hardware implementations by pointing out common instructions or instructions often executed together that can benefit from additional dedicated hardware. Send directives to the assembler for correctly interpreting the human-written assembly code. Serve as mnemonics for the programmer in order to remember common instructions or procedures, but are not used in actual assembly code.
Can a program unconditionally jump to any absolute address in the whole memory address space?
(consider a starting point of all registers set to zero) Yes, but using two instructions. Yes, with a single instruction. No, addressing is always relative to PC for supporting position-independent code.
A RISC-V core implementation must contain only one memory chip, containing both the Data Memory and Instruction Memory.
True False.
The "I" base extension is the only mandatory extension, other than its reduced “E” extension.
True False.
Instructions from the C extension are functionally equivalent to pseudoinstructions.
True False.
Can a 64 bit floating point register file be implemented in a RV32 architecture, therefore coexisting with a 32 bit integer register file?
Yes Yes, with limitations No.
The A Extension for atomic operations is required in order to make the system respect the RISC-V memory model.
True False.
Incoherent memory can be consistent with the memory model.
True False.
FENCE and FENCE.I instructions do the same thing on different memories.
True False.
A proposed extension marked as "Frozen" means that it cannot accept modifications anymore.
True False.
What can never happen while handling a trap?
Another trap has to be handled Code running in a higher privilege mode than code running before the exception is executed Code running in the same privilege mode as the code running before the exception is executed Code running in a lower privilege than code running before the exception mode is executed The system crashes and execution stops The system enters Debug mode.
Does RISC-V support hypervisor nesting (running a hypervisor on top of another hypervisor)?
Always (with the Hypervisor extension) Never Only with an additional extension other than the Hypervisor extension.
If PMP is supported, PMAs are no longer needed in order to safely handle memory.
True False.
Assembly language is a human-readable version of machine language.
True False.
What does the following RISC-V instruction mean?
add x6, x8, x10 Add the contents of registers x8 and x10, and store the result in x6 Add the contents of registers x6 and x8, and store the result in x10 Add the contents of registers x8, x10, and x6, and store the result in x6 That instruction format is not supported by RISC-V.
What is the mnemonic for the RISC-V instruction or pseudoinstruction that performs an unconditional jump/branch to some target?
b bra j jmp.
A label in assembly language occupies a memory address.
True False.
Which ISA extension defines instructions to manipulate CSRs?
The C ISA extension The Zicsr ISA extension The Zifencei ISA extension Actually, these instructions are part of the Base Integer ISA.
The RV32I Base Integer ISA includes an instruction to load an arbitrary 32-bit immediate value to a register.
True False.
Which naming convention of registers is supported by the assembler?
Which naming convention of registers is supported by the assembler?
Only the ABI (software side) names, like ra, t3, and a2 Only the numbered (hardware side) names, like x0, x3, and x20 Actually, there is only one naming convention of registers: From r0, through r31.
Which assembler directive is used to specify the start of the memory section where global variables will be stored?
.globl .rodata .text .data.
Which assembler directive is used to specify the start of the memory section where machine code will be stored?
.data .text .rodata .globl.
What is wrong with the following assembly code? The code is supposed to take two 4-byte variables from memory (a and b) at addresses 0x1000 and 0x1004 respectively, add them, and store the result in a third 4-byte variable c, at address 0x1008.
1 lui t0, 1 # t0 points to 0x1000
2 lw t1, 0(t0) # Load a into t1
3 lw t2, 4(t0) # Load b into t2
4 addi t3, t1, t2 # t3 <- t1 + t2
5 sw t3, 8(t0) # Store t3 into c The addition instruction in line 4 should be add, not addi. In line 1, making t0 point to 0x1000 requires two instructions.
The offsets in lines 3 and 5 are incorrect.
Nothing is wrong with the code.
What is wrong with the following assembly code?
(The code is supposed to increment the 4-byte integer i by 5, and the 1-byte character c by 10.)
.data
i: .word 33
c: .byte 'x'
.text
.align 2
.globl main
main:
1 la t0, i # t0 points to i
2 lw t1, 0(t0) # t1 implements i
3 lb t2, 4(t0) # t2 implements c
4
5 addi t1, t1, 5 # i += 5;
6 addi t2, t2, 10 # c += 10;
7
8 sw t1, 0(t0) # Update i
9 sb t2, 4(t0) # Update c In line 1, there is no such thing as the la instruction.
The addition instructions in lines 5 and 6 should be addi, not add.
The offsets in lines 2, 3, 8, and 9 are incorrect. Nothing is wrong with the code.
How many instructions are executed in the following code snippet?
.text
.align 2
.globl main
main:
addi t0, x0, 0x100 # Set s0 to point to address 0x100
addi t4, x0, 10 # Initialize t4 to 10
sw t4, 0(t0) # Store t4 where t0 points
addi t4, t4, 9 # Add 9 to t4
sw t4, 4(t0) # Store t4 where t0+4 points
addi t4, t4, 13 # Add 13 to t4
sw t4, 8(t0) # Store t4 where t0+8 points
addi t4, t4, -1 # Subtract 1 from t4
sw t4, 12(t0) # Store t4 where t0+12 points 9 10 13 It is impossible to know.
How many instructions are executed in the following code snippet?
stage1:
addi t0, x0, 0x100 # Set s0 to point to address 0x100
addi t4, x0, 10 # Initialize t4 to 10
j stage2
sw t4, 0(t0) # Store t4 where t0 points
addi t4, t4, 9 # Add 9 to t4
sw t4, 4(t0) # Store t4 where t0+4 points
stage2:
addi t4, t4, 13 # Add 13 to t4
sw t4, 8(t0) # Store t4 where t0+8 points
addi t4, t4, -1 # Subtract 1 from t4
sw t4, 12(t0) # Store t4 where t0+12 points 7 10 12 It is impossible to know.
How many instructions are executed in the following code snippet?
stage1:
addi t0, x0, 0x100 # Set s0 to point to address 0x100
addi t4, x0, 10 # Initialize t4 to 10
beq t1, t2, stage2
sw t4, 0(t0) # Store t4 where t0 points
addi t4, t4, 9 # Add 9 to t4
sw t4, 4(t0) # Store t4 where t0+4 points
stage2:
sw t4, 8(t0) # Store t4 where t0+8 points
addi t4, t4, -1 # Subtract 1 from t4
sw t4, 12(t0) # Store t4 where t0+12 points 6 9 12 It is impossible to know.
How many instructions are executed in the following code snippet?
1 .text
2 .align 2
3 .globl main
4
5 main:
6 addi t0, x0, 100 # Initialize t0 to 100
7 addi t1, x0, 0x0 # Initialize t1 to 0
8 loop:
9 add t1, t1, t0 # Increment t1 by t0
10 addi t0, t0, -25 # Decrement t0 by 25
11 bnez t0, loop # If t0 is not zero, go to loop
12 lui t0, 0x1 # Set t0 to point to address 0x1000
13 addi t0, t0, 0x100 # Add 0x100 to t0, to make it point to 0x1100
14 sw t1, 0(t0) # Store the result in 0x1100 6 9 12 17.
Which of the following is NOT a pseudoinstruction?
j offset lui rd, immediate nop ret.
Which tool can be used to view the (dis)assembly of an object file, e.g., example.o?
cat dasm
objdump.
Which mode can be used by the Qemu in order to simulate only a single program on a different architecture than the target architecture?
System-mode User-mode.
What is the effect on the executable of compiling with the option -pg for profiling?
Extra code is inserted that allows counting how much time the program is inside a function during execution Extra code is inserted that allows counting how many memory transfer instructions are done during execution.
What is the purpose of the program gprof?
To execute a profiled program and to collect information To analyze information collected during execution of a profiled program.
Consider the following output obtained by profiling and given by gprof:
Each sample counts as 0.01 seconds.
% cumulative self self total
time seconds seconds calls ns/call
ns/call name
56.25 0.09 0.09 2000000 45.00
60.00 func
25.00 0.13 0.04
main
18.75 0.16 0.03 1165832 25.73
25.73 add
Which statement is correct? 60 ns on average was spent inside the function func per call. 60 ns on average was spent inside the function func and its descendents per call. 25% of the running time was spent inside the function func. The function func was called 1,165,832 times.
Which of the following function attributes defines a machine interrupt handler?
__attribute__ ((interrupt ("machine"))) __attribute__ ((machine ("interrupt")))
__attribute__ ((“machine interrupt”)))
__attribute__ ((interrupt ("user"))).
Which of the following instructions is inserted at the end of a function call declared as __attribute__ ((interrupt ("supervisor")))?
mret sret.
Why is the calling convention of the application binary interface important?
It defines a standard way to re(store) registers by function calls It provides a definition of pragmas of RISC-V specific optimizations It describes the inline assembly usage.
What defines the correct way to use the register while programming or understanding assembly code?
Knowing the keyword of inline assembly The ABI provides alias names of registers that allow better understanding of a registers use in context The tool opt of the llvm toolchain Using a profiler to assess the program's performance.
Which of the following instructions is very likely to be inside a prologue of a function?
addi sp, sp, -32 addi sp, sp, 32 ld s0, 16(sp) mv a0, a5.
Consider the following inline assembly instructions where the clobbers are missing:
asm volatile(
"addi a1, x0, 1 \n"
"add a2, a1, %1\n"
"add %0, %1, a2 \n"
:"=r"(x)
:"r"(y)
: );
Which is the correct line for the clobbers? "%0", "%1" "a1", "a2" "t1", "t2".
If a function f calls a function g, what should be done with the register s0 according to the calling convention?
The coding convention makes no statement and it is up to the developer The function f should store the register s0 before the call of g and restore after it The function g should store the register s0 in its prologue and restore it in its epilogue.
The local variable x is in the scope of a function f: void f() { int x; …}
What is NOT a plausible assembly result of the compilation? There is a register used for the variable x in the function There is a relocation entry of the variable x for addressing it There is memory reserved on the stack for the variable x in the function.
According to the calling convention, which register contains the return value of a function?
x5 x8 x10.
What is the distinction between compiling using GCC or using LLVM?
LLVM follows a different approach than GCC by an intermediate representation that can be analyzed and optimized separately. There is no distinction at all, both provide the same tools in very similar technical ways.
What is an advantage of using an intermediate representation?
An intermediate representation can be used as any other high-level language and is easy to program. Using an intermediate representation allows optimizing the code target-independently.
Clang can control all phases of the compiling process from frontend to backend. Where does the assembler (assembling step) belong?
Backend Frontend Neither the frontend nor the backend.
What does the tool lli do?
The tool lli allows to interpret a program given as an intermediate representation. The tool lli allows for interactive control of the llvm compiler. The tool lli does not exist.
Which of the following are characteristics of virtual memory?
Select all answers that apply
Incorrect Answer It can contain software memory cells not directly mapped to a hardware memory cell, but still addressable and usable by higher level software.
It has a single address space. It is divided into pages, 4 kilobytes long sections of continuous memory. It isolates software running above it requiring addresses to be translated by the operating system.
What should an operating system do?
Manage and abstract hardware, and provide services to applications Only manage and abstract hardware Only provide services to applications.
Which of the following inline assembly instructions are correct?
Select all answers that apply
Incorrect Answer asm volatile("csrrwi x0, mstatus, %0" ::"r"(0x8));
asm volatile("csrrw x0, mstatus, %0" ::"r"(0x8)) asm volatile("csrrwi x0, mstatus, %0" ::"i"(0x8));.
A page table is necessary for virtual memory.
True False.
The OS will always ensure that virtual addresses allocated to applications will be mapped.
True False.
Which of the following statements about mutexes in a RISC-V OS is correct?
Mutex is a type of semaphore used for inter-process communication. Mutex is a mechanism for allocating physical memory. Mutex is a mechanism to synchronize access to shared resources.
Which of the following is commonly used in a RISC-V OS as synchronization primitives?
Mutex Semaphore Mutex & Semaphore.
Which of the following instructions will be used to switch from S-mode OS to a U-mode application?
csrrw ecall sret.
Which privileged modes can an SBI implementation run?
M-mode only M-mode and HS-mode M-mode, HS-mode, and VS-mode All privilege modes.
What is OpenSBI?
A hypervisor to run multiple RISC-V OSes A reference implementation of the SBI specification A RISC-V proprietary operating system A software development kit for developing RISC-V applications.
What do the Medium low code models allow the code to address?
Only the RV32 address space, no RV64 address space The whole RV32 address space, or the lower 4GiB of RV64 address space The whole RV32 address space, or the lower 2GiB and highest 2GiB of RV64 address space.
Assuming we have an OS in S-mode and OpenSBI in M-mode, how can the OS invoke the SBI functionalities?
Invoking the ecall instruction with proper parameters Invoking the sret instruction with proper parameters It can not invoke the OpenSBI because they are in different privileged modes.
Is it possible to disable SMAP in a RISC-V OS (paged virtual memory enabled)? Why?
Yes, it is possible by setting SUM bit to 0. Yes, it is possible by setting SUM (permit Supervisor User Memory access) bit to 1. No, it is impossible.
Is it possible to disable SMEP in a RISC-V OS (paged virtual memory enabled)? Why?
Yes, it is possible by setting SUM bit to 0. Yes, it is possible by setting SUM (permit Supervisor User Memory access) bit to 1. No, it is impossible.
Which of the following registers are typically saved during a context switch in RISC-V OS?
Floating-point registers only General-purpose-registers only Both general-purpose and floating-point registers None of the above.
Which instructions are typically used to save and restore the state of a process during a context switch?
sw(sd) and lw(ld) instructions
ecall and sret instructions.
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